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preliminary vcxo and synchronous ethernet jitter attenuator ics810251i idt? / ics? vcxo and jitter attenuator 1 ics810251agi rev. a november 14, 2007 general description the ics810251i is a high-performance, low jitter/ low phase noise vcxo and jitter attenuator for synchronous ethernet applications. applications ? synchronous ethernet v0.39a ? end equipment compliant with std ieee 802.039a features ? one single-ended output (lvcmos or lvttl levels), output impedance: 15 ? ? phase jitter attenuation by the vcxo-pll using a 25mhz pullable external crystal (xtal) ? input frequencies: 25mhz or 125mhz ? output frequency: 25mhz ? pll loop bandwidth adjustable by external components ? absolute pull range is 50 ppm (using the internal oscillator) ? 25mhz or 125mhz auto input frequency detect ? output frequency free runs at 25m hz if no input is present - ppm accuracy is dependent on external xtal spec ? full 3.3v or 2.5v supply voltage ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages. hiperclocks? ic s ics810251i 16-lead tssop 4.4mm x 5.0mm x 0.925mm package body g package top view pin assignment block diagram vcxo-pll lf0 lf1 (external loop filter inputs.) xtal_in xtal_out pre- divider pfd cp vcxo 25mhz 25mhz clk_in q (25mhz or 125mhz input frequency auto detect) (1 or 5) oe 1 0 pll_sel 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 oe q reserved gnd pll_sel clk_in lf1 lf0 gnd xtal_in xtal_out g n d v ddo v dda v dd v dd the design target information presented herein represents a prod uct currently in design or being considered for design. the not ed characteristics are design targets. integrated device technologies, incorporated (idt) reserves the right to change any circuitry or specifications without notice.
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 2 ics810251agi rev. a november 14, 2007 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 pll_sel input pullup when logic high, the vcxo-pll is ena bled. when low, the vcxo-pll is in bypass mode. lvcmos/lvttl interface levels. 2, 9, 12 gnd power power supply ground. 3 reserved reserved reserved pin. leave floating and not connected 4 q output single-ended clock output. lvcmos/ lvttl interface levels. 5v ddo power output power supply pin. 6 oe input pullup output enable pin for q output. lvcmos/lvttl interface levels. 7v dda power analog supply pin. 8, 15 v dd power power supply pins. 10, 11 xtal_out, xtal_in input vcxo crystal oscillator interface. xta l_in is the input. xtal_out is the output. 13, 14 lf0, lf1 analog input/ output single-ended clock input. lvcmos/ lvttl interface levels. 16 clk_in input pulldown single-ended clock input. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf c pd power dissipation capacitance v dd, v ddo = 3.465v 8 pf v dd, v ddo = 2.625v 5 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance v ddo = 3.3v5% 15 ? v ddo = 2.5v5% 20 ?
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 3 ics810251agi rev. a november 14, 2007 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c table 3b. power supply dc characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 92.4 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.05 3.3 v dd v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 30 ma i dda analog supply current 5 ma i ddo output supply current no load 0 ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage v dd ? 0.05 2.5 v dd v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 30 ma i dda analog supply current 5 ma i ddo output supply current no load 0 ma
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 4 ics810251agi rev. a november 14, 2007 table 3c. lvcmos/lvttl dc characteristics, v dd = v ddo = 3.3v 5% or 2.5v 5%, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information section. load test circuit diagrams. ac electrical characteristics table 4a. ac characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note 1: this parameter is defined in accordance with jedec standard 65. note 2: please refer to the phase noise plot. symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.465v 2 v dd + 0.3 v v dd = 2.625v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v v dd = 2.625v -0.3 0.7 v i ih input high current clk_in v dd = v in = 3.465v or 2.625v 150 a oe, pll_sel v dd = v in = 3.465v or 2.625v 5 a i il input low current clk_in v dd = 3.465v or 2.625v, v in = 0v -5 a oe, pll_sel v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 v ddo = 3.3v 5% 2.6 v v ddo = 2.5v 5% 1.8 v v ol output low voltage; note 1 v ddo = 3.3v 5% or 2.5v 5% 0.5 v parameter symbol test conditi ons minimum typical maximum units f ref input reference frequency 25 mhz 125 mhz f vco vcxo-pll frequency range 25 mhz f out output frequency 25 mhz t jit(cc) cycle-to-cycle jitter; note 1 tbd ps tjit rms phase jitter (random); note 2 integration range: 12khz ? 10mhz (f out = 25mhz) 0.22 1 ps t jit(per) period jitter tbd ps t r / t f output rise/fall time 20% to 80% 845 ps odc output duty cycle 45 50 55 %
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 5 ics810251agi rev. a november 14, 2007 table 4b. ac characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c note 1: this parameter is defined in accordance with jedec standard 65. note 2: please refer to the phase noise plot. parameter symbol test conditions minimum typical maximum units f ref input reference frequency 25 mhz 125 mhz f vco vcxo-pll frequency range 25 mhz f out output frequency 25 mhz t jit(cc) cycle-to-cycle jitter; note 1 tbd ps tjit rms phase jitter (random); note 2 integration range: 12khz ? 10mhz (f out = 25mhz) 0.24 1 ps t jit(per) period jitter tbd ps t r / t f output rise/fall time 20% to 80% 1330 ps odc output duty cycle 45 50 55 %
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 6 ics810251agi rev. a november 14, 2007 typical phase noise at 25mhz (3.3v) typical phase noise at 25mhz (2.5v) ethernet filter phase noise result by adding an ethernet filter to raw data raw phase noise data ? ? ? 25mhz rms phase jitter (random) 12khz to 10mhz = 0.22ps (typical) noise power dbc hz offset frequency (hz) ethernet filter phase noise result by adding an ethernet filter to raw data raw phase noise data ? ? ? 25mhz rms phase jitter (random) 12khz to 10mhz = 0.24ps (typical) noise power dbc hz offset frequency (hz)
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 7 ics810251agi rev. a november 14, 2007 parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit cycle-to-cycle jitter period jitter 2.5v core/2.5v lvcmos output load ac test circuit rms phase jitter output rise/fall time scope qx lvcmos gnd v dd, 1.65v5% -1.65v5% v ddo v dda 1.65v5% ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles q v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram scope qx lvcmos gnd v dd, 1.25v5% -1.25v5% v ddo 1.25v5% v dda phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power clock outputs 20% 80% 80% 20% t r t f
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 8 ics810251agi rev. a november 14, 2007 parameter measurement in formation, continued output duty cycle/pulse width/period application information recommendations for unused input pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. t period t pw t period odc = v ddo 2 x 100% t pw q
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 9 ics810251agi rev. a november 14, 2007 schematic example figure 1 shows an example of the 810251i application schematic. in this example, the device is operated either at v dd = 3.3v or 2.5v. the decoupling capacitors should be located as close as possible to the power pin. the input is driven by an lvcmos driver. an optional 3-pole filter can also be us ed for additional spur reduction. it is recommended that the loop filt er components be laid out for the 3-pole option. this will also allo w the 2-pole filter to be used. figure 1. p.c. ics810251i schematic example
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 10 ics810251agi rev. a november 14, 2007 application information vcxo-pll e xternal c omponents choosing the correct external components and having a proper printed circuit board (pcb) layout is a key task for quality operation of the vcxo-pll. in choosing a crystal, special precaution must be taken with the package and load capacitance (c l ). in addition, frequency, accuracy and temperature range must also be considered. since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like hc49 be used. generally, a metal-canned package has a larger pulling range than a surface mounted device (smd). for crystal selection information, refer to the vcxo crystal selection application note. the crystal?s load capacitance c l characteristic determines its resonating frequency and is closely related to the vcxo tuning range. the total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, ic package lead capacitance, internal varactor capacitance and any installed tuning capacitors (c tune ). if the crystal c l is greater than the total external capacitance, the vcxo will oscillate at a higher frequency than the crystal specification. if the crystal c l is lower than the total external capacitance, the vcxo will oscill ate at a lower frequency than the crystal specification. in either case, the absolute tuning range is reduced. the correct value of c l is dependant on the characteristics of the vcxo. the recommended c l in the crystal parameter table balances the tuning range by centering the tuning curve. the vcxo-pll loop bandwidth selection table shows r s , c s and c p values for recommended high, mid and low loop bandwidth configurations. the device has been characterized using these parameters. for other configurations, refer to the loop filter component selection for vcxo based plls application note. the crystal and external loop filter components should be kept as close as possible to the device. loop filter and crystal traces should be kept short and separated from each other. other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. vcxo characteristics table vcxo-pll loop bandwidth selection table crystal characteristics lf0 lf1 xtal_in xtal_out r s c s c p c tune c tune 25mhz symbol parameter typical units k vcxo vcxo gain 15000 hz/v c v_low low varactor capacitance 9.8 pf c v_high high varactor capacitance 22.7 pf bandwidth crystal frequency (mhz) r s (k ? )c s (f) c p (f) 246hz (low) 25 0.4 10 0.01 616hz (mid) 25 1.0 10 0.001 1000hz (high) 25 1.65 10 0.001 symbol parameter test conditions minimum typical maximum units mode of oscillation fundamental f n frequency 25 mhz f t frequency tolerance 20 ppm f s frequency stability 20 ppm operating temperature range -40 +85 0 c c l load capacitance 10 pf c o shunt capacitance 4 pf c o / c 1 pullability ratio 220 240 esr equivalent series resistance 20 ? drive level 1mw aging @ 25 0 c 3 per year ppm
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 11 ics810251agi rev. a november 14, 2007 reliability information table 5. ja vs. air flow table for a 16 lead tssop transistor count the transistor count for ics810251i: 937 package outline and package dimension package outline - g suffix for 16 lead tssop table 6. package dimensions for 16 lead tssop reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 92.4c/w 88.0c/w 85.9c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics810251i vcxo and synchronous ethernet ji tter attenuator preliminary idt? / ics? vcxo and jitter attenuator 12 ics810251agi rev. a november 14, 2007 ordering information table 7. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 810251agi tbd 16 lead tssop tube -40 c to 85 c 810251agit tbd 16 lead tssop 2500 tape & reel -40 c to 85 c 810251agilf 810251al 16 lead ?lead-free? tssop tube -40 c to 85 c 810251agilft 810251al 16 lead ?lead-free? tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support device s or critical medical instruments.
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